The present invention relates to a packet switching system and more precisely to the type of packet switching system which is provided with a packet handler, corresponding to each incoming circuit of the system, which is capable of processing the header of a packet and deciding its outgoing route of the packet and in which the switching of packets to their outgoing circuits is realized through a cross-point switch for circuit switching which makes connections between the packet handlers and outgoing circuits of the packet switching system. Thus, the necessity of storing all the bits of individual packets in the switching system is eliminated to improve the efficiency of packet processing. The present packet switching system can also deal with circuit-switched calls sharing a cross-point switch with packet-switched calls.
One example of the structure of the conventional packet switching system is shown in FIG. 1 wherein numerals 1, 2, 3 and 4 designate packet communication circuits, LT.sub.1 through LT.sub.4 designate circuit terminating units, and numeral 40 designates a packet processing unit. Further, BM in the packet processing unit designates a buffer memory which is commonly used for packets to all the outgoing routes and CPU designates a central processing unit. In this structure, the circuit terminating units LT.sub.1 through LT.sub.4 control signal transmission/reception and error correction (e.g., by HDLC procedures) and all received packets are once stored in the common buffer memory BM. The stored packets are then analyzed to determine their outgoing routes under the control of the central processing unit CPU and are transmitted over the circuits of the outgoing routes via the circuit terminating units LT.sub.1 through LT.sub.4.
Another example of the conventional packet switching system is shown in FIG. 2. In FIG. 2, numerals 1 through 3, 11 through 13 and 21 through 23 designate packet communication circuits, respectively, LT.sub.1 through LT.sub.3 designate circuit terminating units. Numeral 50 designates a control processor and numeral 60 designates an internal communication bus. In the shown structure, the packet processing units 41 through 43 control the buffer memory and process packet headers. The control processor 50 controls the entire system and performs processings which are common throughout the system such as packet call routing control.
However, the conventional packet switching systems shown in FIGS. 1 and 2 have had such disadvantages that the control of the centralized buffer memory for storage of all the packets therein and the link-by-link sequence and flow controls of the packets have been complicated; it has been difficult to process a large number of packets efficiently because the amount of packet processing load has been large; and as the whole packets must have been once stored in the memory, the delay of packet transfer time has been accelerated.